The present invention generally relates to memory supervision, and more particularly to a method and system for testing a memory in operation.
Memory devices are found in numerous applications of all modem technologies. They are widely used in different fields of electronics and communication. In the specific field of telecommunication, memory devices play an important role in communication switches.
A communication switch generally comprises speech stores for storing user data, and control stores for storing control information that control the switching of the user data. It is of course important that the speech stores and control stores operate properly, and in operation, the speech stores and control stores should be supervised so that they can be promptly replaced in the case of a hardware failure.
According to a particular type of switching called circuit switching, the user data is normally assigned to time slots that are arranged in frames. In the communication switch, the user data is moved between different time slots and frames. This is done by storing the user data in speech stores and storing control information in control stores.
According to the prior art, a through connection test (TCT) is performed for each connection in order to ensure that data in an incoming time slot reaches an outgoing time slot. In a TCT, a parity error is inserted in the incoming time slot to be tested, and the connection path which may consist of speech stores, multiplexors and interfaces is supervised by checking that the parity error reaches the corresponding outgoing time slot.
Although the through connection test works satisfactory in many respects, the TCT-approach has a number of drawbacks:
A real parity error may erroneously fail the TCT;
The TCT only checks the path during the setup of a connection;
The software has to be coordinated to control both inputs and outputs;
The method requires a significant delay and is not scaleable; and
In a speech store or control store based on a RAM (Random Access Memory), there might be stuck-at faults which escape the usual parity checks; a situation which could result in a data transmission problem, the source of which is difficult to localize.
U.S. Pat. No. 5,436,912 relates to a circuit arrangement for testing a semiconductor memory by means of parallel tests using various test bit patterns, in which any n-tuples of test bits can be written into at least one n-bit long register. The n-tuple of test bits located in each register can be written via data lines of the semiconductor memory into a multiplicity of memory cell n-tuples having a common word-line. The n-tuple of test bits in each register can be supplied to a multiplicity of comparator circuits. The bit patterns of the memory cell n-tuples having a common word line can be read out via data lines and with which the n-tuples of test bits can be compared in the comparator circuits. The comparator outputs are combined by pairs of wired OR-lines to form an address matrix constructed so as to enable location of faulty individual memory cells or faulty memory cell n-tuples.
European Patent Application 0,276,047 relates to a semiconductor integrated circuit device in which a program for information processing is stored in a read only memory formed of an EPROM (electrically programmable read only memory). To improve the reliability of the integrated circuit device, the EPROM has a storage area formed by dummy storage elements distinct from the normal storage elements of the memory. Access to the dummy storage elements is permitted on the basis of a control signal from an external terminal. The dummy storage elements are used for a test of the write operation of the memory by writing data into those dummy elements such that the data and word lines and the selection circuit for those lines can be tested. By selecting the dummy word or data line, and having the other normal word or data lines deselected, the dummy elements can be tested, thereby permitting testing of the memory even though the other memory elements are not erasable.
A general object of the invention is to find a way to test a memory, such as a RAM, while it is in operation.
It is an object of the invention is to provide a method and system for testing a memory in operation.
In particular, it is desirable to continuously check the function of a speech store or a control store in operation in a communication switch.
These and other objects are met by the invention as defined by the accompanying patent claims.
According to a general inventive concept, a storage unit is used to temporarily free one memory location in the memory, making it possible to check this memory location for bit errors. A test pattern is written into the memory location to be tested and read out again in coordination with the normal operation of the memory. If the pattern read from the test location does not match the written test pattern, an alarm is raised.
All memory locations in the memory can be tested to make sure that there are no bit errors in the memory. This process may be active all the time, with or without data traffic through the memory.
The solution according to the invention causes no extra delay, and demands no waiting periods. The complete memory can be checked for both stuck-at faults and crosstalk, not only locations currently in use. In addition, real parity errors do not affect the memory check.
In the case of a speech store in operation in a communication switch, a preferred embodiment of the invention incorporates a latch unit provided on the input side of the speech store. The data intended for a predetermined memory location in the speech store is temporarily stored in the latch unit, and instead a test pattern is stored in the speech store at the predetermined memory location. The test pattern can be checked when the memory location that holds the test pattern is selected and the contents of this location is requested in the operation of the communication switch, or when no data at all is requested from the speech store. Since, the test pattern has been written to this location, the correct data for this memory location is currently stored in the latch unit. Now, the data stored in the latch unit is forwarded as requested output data, and the test pattern is read and checked by a control unit.
With this arrangement, the maximum number of memory accesses will not increase, implicating that the highest read/write frequency can be maintained at the same level compared to prior art solutions. Besides, it is possible to reduce the number of faulty data words that are transmitted before a speech store experiencing a hardware failure is replaced. However, compared to the conventional through connection test, it should be noted that the complete connection path is not checked. Multiplexers and other interfaces must be maintained by other means.
In the case of a control store in operation in a communication switch, a preferred embodiment of the invention incorporates a latch unit provided on the output side of the control store. The data from a predetermined memory location in the control store is temporarily stored in the latch unit. When data has been read out of the predetermined memory location and stored in the latch unit, that location will be xe2x80x9cfreexe2x80x9d and a test pattern can be written into the control store at the predetermined location. When the data in the predetermined test location is requested in the operation of the communication switch, the data stored in the latch unit is forwarded as requested output data and the content of the predetermined memory location is read and checked by a control unit. When the test has been completed, the data stored in the latch unit should be stored in the predetermined memory location once again, so that it can be read from the control store at a later time in accordance with the instructions from the control system of the communication switch. If there is an attempt to write new operational data to the memory location during the test, the new incoming data needs to be stored in the latch unit on the output side of the control store. The new data thus replaces the data previously stored in the latch unit.
Depending on whether the memory is a speech store or a control store, the implementation will be somewhat different. This implementational difference is due to the fact that when a control store is in operation data is constantly read from the control store and data is written to the control store only in some clock cycles when the contents of the control store need to be updated, while for a speech store data is constantly written into the speech store and the data is subsequently read from the speech store in accordance with the control information stored in the control store.
To summarize, the invention offers the following advantages:
continuous supervision of a memory in operation;
no extra delay;
possibility to check the complete memory for both stuck-at faults and crosstalk, not only locations currently in use;
real parity errors do not affect the memory check;
the maximum number of memory accesses will not increase; and
reduction of the number of faulty data words that are transmitted before a memory experiencing a hardware failure is replaced.
Other advantages offered by the present invention will be appreciated upon reading of the below description of the embodiments of the invention.